Posts tagged with Paper

ExaNoDe @ DSD 2017

in Paper

Today, I presented the ExaNoDe positioning paper at the Euromicro DSD conference in Vienna. VOSYS is leading the dissemination work package of ExaNoDe, and coordinated the writing of the paper.

Vienna

The paper is entitled Paving the way towards a highly energy-efficient and highly integrated compute node for the Exascale revolution: the ExaNode approach:

Power consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able to provide the requested level of density and power efficiency to realise an operational Exascale machine. A disruptive change in the hardware design and integration process is needed in order to cope with the requirements of this forthcoming computing target. This paper presents the ExaNoDe H2020 research project aiming to design a highly energy efficient and highly integrated heterogeneous compute node targeting Exascale level computing, mixing low-power processors, heterogeneous co-processors and using advanced hardware integration technologies with the novel UNIMEM Global Address Space memory system.

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BOAST: A metaprogramming framework to produce portable and efficient computing kernels for HPC applications

in Paper

The journal article I co-authored with B. Videau within the Mont-Blanc project is now published in The International Journal of High Performance Computing Applications.

The part I wrote are related to the porting of Specfem3D to OpenCL, and testing non-regression using debugging traces.

  • 5.3 Porting SPECFEM3D application kernels: From CUDA to OpenCL using BOAST
  • 4.3 Non-regression testing using trace debugging

Mont-Blanc

The portability of real high-performance computing (HPC) applications on new platforms is an open and very delicate problem. Especially, the performance portability of the underlying computing kernels is problematic as they need to be tuned for each and every platform the application encounters. This article presents BOAST, a metaprogramming framework dedicated to computing kernels. BOAST allows the description of a kernel and its possible optimizations using a domain-specific language. BOAST runtime will then compare the different versions’performance as well as verify their exactness. BOAST is applied to three use cases: a Laplace kernel in OpenCL and two HPC applications BigDFT (electronic density computation) and SPECFEM3D (seismic and wave propagation).

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Interactive Runtime Verification - When Interactive Debugging Meets Runtime Verification

in Paper

The article I co-authored with R. Jakse got accepted at the 28th ISSRE conference. It will take place in Toulouse, France, on October 23-26th, 2017.

ISSRE

Monitoring is the study of a system at runtime, looking for input and output events to discover, check or enforce behavioral properties. Interactive debugging is the study of a system at runtime in order to discover and understand its bugs and fix them, inspecting interactively its internal state.

Interactive Runtime Verification (i-RV) combines monitoring and interactive debugging. We define an efficient and convenient way to check behavioral properties automatically on a program using a debugger. We aim at helping bug discovery while keeping the classical debugging techniques and interactivity, which allow understanding and fixing bugs.

SAC 2013

in Paper, Poster

Last week, I presented a short paper and a poster at SAC 2013, Coimbra, Portugal. They were entitled:

A Novel Approach for Interactive Debugging of Dynamic Dataflow Embedded Applications

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